#Synplify pro batch mode how to
#Synplify pro batch mode software

Select Files to Add to Project Dialog Box The HDL files have now been added to the project.įigure 3. The Select Files to Add to Project dialog box appears (see Figure 3).įrom the Select Files to Add to Project dialog box, click the appropriate HDL file(s). Turn on Disable I/O Insertion.įrom the Synplify window, click Add. Turn-on the Disable I/O Insertion option.įigure 2. At this time, the LogicLock design flow supports Cyclone™, Stratix™, APEXTM II, APEX 20KE, APEX 20KC, and ARM®-based ExcaliburTM devices. Setting the Target Technology To set the target technology:įrom the Options for Implementation dialog box (see Figure 2), set the target technology (Technology pull-down menu) to a family that supports the LogicLock design flow. Set the target technology Read-in files Perform synthesis Generating VQM Files for Lower-Level Modules To generate VQM files for lower-level modules, the following steps must be completed: ■ ■ ■ By generating multiple VQM files, you can take advantage of the LogicLock incremental design flow in the Quartus II software.

#Synplify pro batch mode how to

This section describes how to generate multiple VQM files in the Synplify software. – In the Attributes tab, set syn_netlist_hierarchy to 0. – Enter the clock frequency with SCOPE to ensure that the design is correctly optimized. – The constraints that affect lower-level modules should be the same as the constraints used when optimizing lower-level modules separately. – Black-box lower-level modules in the top-level design. Turn-off Disable I/O Insertion for the target technology. – Modules may include black-box instantiations of lower-level modules that are also maintained as separate VQM files. Turn-on Disable I/O Insertion for the target technology. When synthesizing the lower-level modules and top-level design in the Synplify software, follow these guidelines. The top-level design includes black-box instantiations of lower-level modules. To create multiple VQM files in the Synplify software, the general flow requires you to create a separate project for each module that you want to maintain as a separate VQM file and for the top-level design.

#Synplify pro batch mode software

Generating Multiple VQM Files in the Synplify Software The fourth designer, designer TOP, is the system designer who performs the final place-and-route. In this example, there are four designers that are working on the project: designer A works on module A (including module C), designer B works on module B, and designer D works on module D. Synplify and Quartus II LogicLock Design Flowįigure 1. In Figure 1, modules TOP, A, B, C, and D are separate files that are coded in the same HDL language. Figure 1 shows an example design hierarchy that separates several modules into separate VQM files. įor more information on LogicLock regions and the LogicLock design flow, see AN 161: Using the LogicLock Methodology in the Quartus II Design Software.

To obtain the Synplicity software, see the Synplicity web site at. This application note applies to Synplify software versions 7.0 and lower. This application note assumes that you are familiar with the Synplify software. This application note describes how to generate multiple VQM files in the Synplify® software that allow you to use the LogicLock design flow in the Quartus II design software. By maintaining separate VQM files, you can place individual modules into LogicLock regions to control placement in the programmable logic device (PLD) and maintain performance of the module even as other modules are added to the project. A hierarchical structure contains one VQM file for the top-level design and one or more VQM files for lower-level modules. This type of hierarchical structure allows the designer to have greater control over placement and preserve fMAX performance. To maximize the benefits from the LogicLockTM incremental design capability of the Quartus® II design software, a new design can be partitioned into a hierarchy of Verilog Quartus mapped (.vqm) files. Synplify and Quartus II LogicLock Design Flow September 2002, ver.